The Fujitsu A64FX had full 512-bit SVE, with 2x 512-bit units per core and HBM memory, which is as CISC as it gets. IIRC was the “widest” CPU that could get the most done per clock, at the time, and the US Department of Energy seemed to love them.
And then you have tiny cores like Intel’s in order ones that are way thinner than ARM designs.
Reality is decoding doesn’t take up much die space these days and stuff is decoded into micro ops anyway. The ISA has an effect, but efficiency/appropriateness for different platforms comes down to design and business decisions more than the ISA.
I mean, that doesn’t mean much.
The Fujitsu A64FX had full 512-bit SVE, with 2x 512-bit units per core and HBM memory, which is as CISC as it gets. IIRC was the “widest” CPU that could get the most done per clock, at the time, and the US Department of Energy seemed to love them.
And then you have tiny cores like Intel’s in order ones that are way thinner than ARM designs.
Reality is decoding doesn’t take up much die space these days and stuff is decoded into micro ops anyway. The ISA has an effect, but efficiency/appropriateness for different platforms comes down to design and business decisions more than the ISA.